1. Technical Field
The present invention belongs to the technical field of semiconductor device manufacturing, relates to a method for manufacturing a semiconductor device, and more especially, to a method for manufacturing a gate-control diode semiconductor device.
2. Description of Related Art
The Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a kind of field effect transistor capable of being widely used in the analog circuits and digital circuits, of which the basic structure is as shown in FIG. 1, including a silicon substrate 101, a gate insulation layer 104 and a gate conductive layer 105 formed on the silicon substrate 101, wherein a drain region 102 and a source region 103 are arranged on both sides of the gate in the substrate 101. When a large enough potential difference is applied between the gate and the source of the MOSFET, the electric field will form induced charges on the surface of the silicon substrate under the gate insulation layer, thus a so-called “inversion channel” is formed. The channel polarity is the same as that of the drain and source. Assume that the drain and the source are of n type, the channel is also of n type. After the formation of the channel, the MOSFET can allow the current to pass through it. The current values passing through the channel of the MOSFET will vary with the voltage values applied on the gate due to its control.
With the continuous development of integrated circuits, the size of the MOSFET becomes smaller and smaller, and the transistor density on unit array becomes higher and higher. Today, the technology node of integrated circuit devices is about 45 nm and the leakage current between the source and the drain of the MOSFET is increasing rapidly with the decrease of channel length. Moreover, the minimum sub-threshold swing (SS) of the traditional MOSFET is limited to 60 mv/dec, which restricts the opening and closing speed of the transistor. On some chips of high integration density, the reduction of the device size means greater SS value. However, the high-speed chips require a smaller SS value to improve the device frequency as well as reduce the chip power consumption. Therefore, when the channel length of the device decreases to less than 30 nm, a new-type of device shall be used to obtain a smaller leakage current and SS value, thus decreasing the chip power consumption.